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Cypress Semiconductor /psoc63 /BLE /BLESS /MT_DELAY_CFG3

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Interpret as MT_DELAY_CFG3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0XTAL_DISABLE_DELAY 0DIG_LDO_DISABLE_DELAY 0VDDR_STABLE_DELAY

Description

MT Delay configuration for state transitions

Fields

XTAL_DISABLE_DELAY

This register specifies the time from switching of logic to Retention LDO in CYBLERD55 to XTAL Disable. This should include the post processing time The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. At the minimum XTAL_DISABLE_DELAY should be the sum of DIG_LDO_DISABLE_DELAY and the powerdown time of ACTIVE_LDO
DIG_LDO_DISABLE_DELAY

This field holds the delay from the time of diabling Digital LDO to the time at which ACTIVE regulator is disabled
VDDR_STABLE_DELAY

This field holds the delay after HVLDO Startup to VDDR Stable. Refer to memo AKK-410

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data